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L6260
4.5 - 5.5V DISK DRIVER SPINDLE & VCM, POWER & CONTROL COMBO'S
GENERAL 5V OPERATION. *REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS SLEEP AND IDLE MODES FOR LOW POWER CONSUMPTION SELECTABLE GAINS FOR BOTH V.C.M. AND SPINDLE 10 BIT (+ SIGN + GAIN ) VCM & 8 BIT SPINDLE DACs HIGH BANDWIDTH SPEED REGULATION LOOP (ONCE PER MECH\ELEC CYCLE ACCURACY) VCM DRIVER CURRENT SENSE CONTROL (VOLTAGE PROPORTIONAL TO CURRENT) 300mA DRIVE CAPABILITY TWO CURRENT RANGES FOR SEEKING AND TRACKING INTERNAL REGISTER FOR POWER AMP CONTROL LINES SPINDLE DRIVER BEMF PROCESSING FOR SENSORLESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY PROGRAMMABLE SLEW-RATE FOR REDUCED E.M.I. 0.8 FOR ANY HALF BRIDGE WORST CASE SYNCHRONOUS RECTIFICATION OF THE B.E.M.F. DURING RETRACT OPERATION BIPOLAR \ TRIPOLAR OPERATION SYNTHESIZED HALL OUTPUTS 1.0 AMP DRIVE CAPABILITY OTHER FUNCTIONS POWER UP SEQUENCING POWER DOWN SEQUENCING LOW VOLTAGE SENSE ACTUATOR RETRACTION DYNAMIC BRAKE THERMAL SHUTDOWN
November 1996
BICMOS TECHNOLOGY
TQFP64 ORDERING NUMBER: L6260
THERMAL & CURRENT PROTECTION DESCRIPTION The L6260 is single chip sensorless (DC) spindle motor and voice coil controllers including power stages suitable for use in small disk drives. These devices have a serial interface for a microprocessor running up to 10 Mega bits per second. There are registers on chip to allow the setting of the desired spindle speed via the on chip Frequency Locked Loop (F.L.L.). No external components are required in the sensor-less operation as the control functions are integrated on chip (e.g. B.E.M.F. processing, digital masking, digital delay and sequencing). The V.C.M. drivers uses a transconductance amplifier, able to provide 2 different current ranges, suitable for seeking and tracking. When a low voltage is detected, a Power On Reset (P.O.R.) is issued and the internal registers are reset, the spindle power circuitry is tri-stated, B.E.M.F. synchronous rectification is enabled, the actuator retracts and then dynamic braking of the spindle is applied. These devices are built in BICMOS technology allowing dense digital circuitry to be combined with MOS\Bipolar power devices.
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L6260
BLOCK DIAGRAM
PARK/V VCM/COMP VCM/I/SNS/1 VCM/I/SNS/2 VCM/PLUS VCM/MINUS VREFOUT VREF/MINUS 177 + BIAS CIRCUIT VCM LOGIC & DAC VOLTAGE TRIPLER POWER MONITOR VCM PARK REGISTER 0 REGISTER 1 REGISTER 2 SDIO SCLK SLOAD R/W SERIAL PORT INTERFACE REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 TEST TRISTATE ATEST DTEST
D94IN087
VVCM/2 VVCM/1 C1LOW C1HIGH C2LOW C2HIGH VHTRIP VLTRIP VPARKOUT CENTER TAP DRIVER CTAP SYNTH/HALL VRECT VSPIN/1 BEMF AMP SPINDLE BLOCK & DAC VSPIN/2 SPN/I/SNS COIL/A COIL/B COIL/C SPIN/GND1 SPIN/GND2 VPDOWN BRK/DLY SPN/I/COMP
DAC/GND UV1 UV2 POR/DLY POR FCLK
SPINDLE LOGIC
CURRENT GENERATOR SPINDLE FLL
SPN/SLEW FLL/RES
CHARGE PUMP
SPD/COMP SPD/COMP/SHT
ANALOG TEST CIRCUIT
DIGITAL TEST CIRCUIT
PIN CONNECTION(Top view)
VFER_MINUS REF OUT SPD COMP SHT SPD COMP SPN1 COMP VPARK OUT SPIN SLEW FLL RES
AGRND DAC GND
GND PARK V
GND
GND
48
GND UV SPN_D SBL_DLY POR_DLY VCM_I_SNS1 VVCM_1 VCM_MINUS VCM_I_SNS2 VCM_PLUS VVCM_2 CTAP ATEST C1HIGH C1LOW TRIPGND C2HIGH
GND
VCC
49
33 32
GND VSPIN_2 VPDOWN COIL_C BRK_DLY SPIN_GND_2 EXTFLL/DTEST COIL_B TRISTATE VSPIN_1 SYNTH_HA LL TEST COIL_A R/W_
64
1
VLTR I P VH R I P T PO R VCM C P M O DI G G N D SD I O VRECT SPN IN S S GN D C2 O W L SLOAD SC K L FCLK GN D VDC
17 16
GND
SPN_GND_1 GND
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L6260
PIN DESCRIPTION Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Power
PIN # 8 41 54 58 23 31 1 15-17 32-34 47-49 18 27 44 45 7 63 PIN NAME VDC VCC VVCM_1 VVCM_2 VSPIN_1 VSPIN_2 GND GND GND GND SPN_GND_1 SPN_GND_2 DAC_GND AGND DIG_GND TRIPGND DESCRIPTION Digital power. Positive nominally 5V or 3V Analog power. Positive nominally 5V or 3V VCM power supply. Positive nominally 5V or 3V Same as above Spindle power pin. Positive nominally 5V or 3V Same as above Ground Ground Ground Ground Ground for spindle circuit As above Ground for all DACs Analog ground Digital ground Voltage tripler ground PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No
Serial Interface & Test Pins
PIN # 12 PIN NAME FCLCK DESCRIPTION System clock. 4-12MHz selectable via the CLK_PRESCALE bit in the System Control Register B (Reg 4 Bit 4). Serial port data I/O running up to 10MHz. For full details of all serial port signals see the Circuit Description section. Serial port clock (max 10Mbits/s) Read / Write signal for serial interface Chip select input. Used to enable one of the test modes. The mode is selcted in conjunction with the TRISTATE pin (see below for more details). Used to enable one of the test modes. The mode is selcted in conjunction with the TEST pin (see below for more details). This pin has no effect on the spindle or VCM drivers, this is a test pin only. Analog test pin. This pin carries the required analog signal to allow external testing. Digital Test Output Pin. This pin also doubles as the Clock input if an external FLL is used. PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR DI Yes No
11
SDIO
DI/O
Yes
Yes
10 19 9 21
SCLK R/W SLOAD TEST
DI DI DI DI
Yes Yes Yes No
No No No No
24
TRISTATE
DI
No
No
60 26
ATEST DTEST
AO DI/O
No No
No No
Test Mode IOMAPPING Test DIGITAL Test* ANALOG Test* TRISTATE Test Normal Operation (non test mode)
TEST pin TRISTATE pin 1 0 1 1 1 1 0 1 0 0
For a detailed description please refer to the Test Circuit section of the CIRCUIT OPERATION portion of this datasheet
* These two test modes operate simultaneously through separate test pins (ATEST and DTEST).
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L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) VCM Driver and DAC
PIN # 53 PIN NAME DESCRIPTION PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR A No No
56 6 57 55 46 35
VCM_I_SNS1 High side of VCM sense resistor network. This pin provides the current to the network as well as sensing the total voltage across both sense resistors. Sensing the total drop across both resistors results in the low transconductance gain feedback used for track following. VCM_I_SNS2 Sensing across the lower VCM sense resistor for high transconductance gain feedback for seek operations. VCM_COMP VCM compensation network. Typically, 200K in series with 100nF is connected from this pin to Ground. VCM_PLUS VCM Power Amplifier positive output terminal VCM_MINUS VCM Power Amplifier negative output terminal PARK_V A resistor conneced between this pin and VCM_PLUS determines the Parking Voltage VPARKOUT Output from the retract circuit. This pin is usually directly connected to the VCM_MINUS.
A A A A A AO
No No No No No No
No No No No No No
Spindle Driver and DAC
PIN # 40 PIN NAME SPN_SLEW DESCRIPTION The External.Spindle Driver Slew Rate resistor (Rslew), typically 250K is connected from this pin to Ground. When in nExternal Slew Rate Mode (System Control Register B, Bit 10=0), the slew rate is determined by: Slew Rate = (0.5V to Rslew) X (DAC slew +1) +20pF DAC slew = System Control Register bits 7 - 9. SPN_I_COMP A seroies RC network from this pin to ground sets the spin driver compensation. Typical a single 4nF capacitor will provide adequate compensation. SPN_I_SNS A current sensing resistor (2.5K Typical ).is connected from this pin to ground. See the Circuit Operation section for details. COIL_A Spindle Power Amplifier output A. Also serves as BEMF sensing for Phase A. COIL_B Spindle Power Amplifier output B. Also serves as BEMF sensing for Phase B. COIL_C Spindle Power Amplifier output C. Also serves as BEMF sensing for Phase C. CTAP Spindle Motor Center Tap connection SYNTH_HALL CMOS level spindle speed output. When SYNHALL (System Control Register B, bit 5) is set to 0, this output switches state at every zero crossing of any phase. With SYNHALL = 1, the output only switches every zero crossing of Phase A. SPD_COMP Change Pump RC network connection pin for FLL mode operation. SPD_COMP_S This pin allows for shorting of to the Charge Pump Network resistor. This operation provides a quick HT charge on the Charge Pump capacitor, reducing settling time once desired speed is reached. Operation is controlled by bit 9 of System Control Register A. FLL_RES Frequency Locked Loop charge pump gain resistor. (Rep), typically 12.5K , is connected from this pin to Ground. Change Pump current is determined by: I = (0.5V to Rcp) X (FLLGAIN DAC +1) FLLGAIN DAC = System Control Register B bits 0-4 PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR A No No
36 14 20 25 29 59 22
A AO A A A A DO
No No No No No No Yes
No No No No No No Yes
37 38
A A
No No
No No
39
A
No
No
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L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Power down sequencing, POR, other voltage pins
PIN # 13 PIN NAME VRECT DESCRIPTION Output of the synchronous rectifier supplying power to the retract circuitry. Filtered by an internal 400pF capacitor. Normally not externally connected. However, if retract command is to be used, a small signal silicon diode must be connected between this pin and Vcc (Cathode to VRECT) to supply the additional current which may be required to brake the VCM. An external parallel RC network from this point to ground sets the Brake dELAY:T = 0.45 RC. Typical values are R = 4M, C=0.1F (0.16sec, delay). Voltage tripler reservoir capacitor. This is used for the brake operation when power is removed from the chip. No DC load allowed. 1F minimum, 10F prefered. Positive terminal of charge pump capacitor. 10nF (typ) for Tripler operation; 330nF (typ0 or Doubler operation Negative terminal of charge pump capacitor. 10nF (typ) for Tripler operation; 330nF (typ) or Doubler operation Positive terminal of charge pump capacitor for Tripler operation. 330nF (typ). Connected tp VHRTRIP for Doubler operation. Negative terminal of charge pump capacitor for Tripler operation. 330nF (typ). Not connected for Doubler operation. An external capacitor from this pin to ground sets the duration of POR after power has been reestablished. T (por) = 32 X C (por) where: C (por) is in pF and T is expresssed in s. Power On Reset. This open drain output goes low when the voltage at either UV1 or UV2 goes below 1.25V. Under voltage detector 1. This defines the VOLTAGE GOOD threshold by comparing the voltage on this pin to the internal 1.25V reference. An external resistor divider network and capacitor filter provides the selection of threshold and supply noise rejection. There is an internal pull-up (2A max). Hysteresis is 20mV. Spindle Disable Delay . A capacitor connected between this pin and Vcc programs the delay between POR and the disabling of the Spindle section.. Delay = 80 xC (C in pF; Delay in s) High tripler/Doubler output. 330nF (typ). 11V max. Low tripler/Doubler output. 330nF (typ). for stability. PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR AO No No
28
BRK_DLY
A
No
No
30
VPDOWN
A
No
No
61
C1HIGH
A
No
No
62
C1LOW
A
No
No
64
C2HIGH
A
No
No
2
C2LOW
A
No
No
52
POR_DLY
A
No
No
5
POR
DO
Yes
No
50
UV1
AI
Yes
No
51
SPN_DSBL_ DLY
AI
Yes
No
4 3
VHTRIP VLTRIP
AO AO
No No
No No
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L6260
PIN DESCRIPTION (continued) Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) Auxiliary Functions
PIN # 42 43* 26 PIN NAME REFOUT DESCRIPTION Output from auxiliary OPAMP. PIN I\O TRI-STATE TYPE MAPPED? @SLEEP/@POR A A DI/O No No No No No No
VREF_MINUS Negative input to auxiliary OPAMP. This is prsent (L6260 only) ONLY on the L6260. EXTFLL/ DTEST See previous description of this pin (Serial interfaca & Test Pin section).
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd , V p max Vin max Vin min Ipeak Idc P tot Tstg,Tj Maximum Supply voltage Maximum input voltage Minimum input voltage Peak sink/source output current DC sink source output current Maximum Total Power Dissipation Maximum storage/junction temperature Parameter Value 6.5 Vdd + 0.3 V GND - 0.5 V 1.5 1.0 1.0 -40 to 150 Units V V V A A W C
POWER DISSIPATION
Symbol Vdd, Vp READY IDLE SLEEP Parameter Supply voltage range QUIESCENT CURRENT QUIESCENT CURRENT QUIESCENT CURRENT VCM ENABLED SPINDLE ENABLED VCM DISABLEDSPINDLE ENABLED VCM DISABLEDSPINDLE DISABLED Test Condition Min. 4.5 Typ. Max. 5.5 20 10 5 Units V mA mA mA
THERMAL DATA
Symbol Rth j-case R th j-amb (*) Parameter Thermal Resistance Junction to Case Thermal Resistance Junction to Case Value 10 41.5 Unit C/W C/W
(*) In typical application with multiplayer printed circuit board.
RECOMMENDED OPERATING CONDITIONS
Symbol Vddn Tamb Tj Supply Voltage Operating Ambient Temperature Junction Temperature Parameter Value 4.5 to 5.5 0 to 70 0 to 125 Unit V C C
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L6260
ELECTRICAL CHARACTERISTICS VCM Driver
Symbol Iocr Iofr Rdson ABEF Rdson CD Vjump Vdeadband Icsbias PSRR BW Parameter Max Current Coarse Range Max Current Fine Range Source & Sink On Resistance Coarse Sink On Resistance Fine Range Current Sense Jump Discontinuity Current Sense Deadband Current Sense Bias Current DC Power Supply Rejection Ratio Current Loop Bandwidth Vdd 4.5 to 5.5 V La = 1mH Ra=40ohms Imax =75mA 50 20 Tj =125 C , Iload = 300 mA C, D VCM drive transistors 1.0 5.0 Test Condition Min. Typ. Max. 300 75 2.5 10.0 1 200 1 Units mA mA Ohms Ohms LSB V A dB KHz
Figure 1: Vjump vs. Deadband
Y(at) UNITS imax 1024 +3 +2 +1 UNITS L.D.D. JT X(in) DAC Register Value -1 -2 -3 +3 +2 +1 +1 +2 +3
D94IN090
Operational Area Nominal
VCM DAC
Symbol R es N.L. I.N.L. CT FSTC Voh Vol PSRR Parameter Resolution 10 Bits Resistive Ladder Plus Sign (1 Bit) Differential Non-Linearity Integral Non - Linearity Conversion Time 0 - 90 % Full Scale Temperature Coefficient High Output Voltage Low output Voltage Power Supply Rejection From Input Of Last Bit (for any change of code) 0 to 125 C 25 C, No Load 25 C, No Load 50 0.240 0.250 Test Condition Unipolar Min. Typ. 11 1 3.0 1.0 250 0.260 100 Max. Units bits LSB LSB s ppm/C V V dB
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L6260
ELECTRICAL CHARACTERISTICS (continued) Spindle Motor
Symbol Io R dson Sink R dson Total dv/dt Parameter Maximum Output Current Sink On Resistance Total drive resistance Rdson sink + Rdson source Voltage Slew Rate Test Condition Tj =125 C , Iload = 1A Tj =125 C, Iload = 1A 0.2 Min. 1 Typ. Max. 0.4 0.8 2 Units A Ohms Ohms V/s
Spindle Current Sense FET
linearity Large signal Linearity small signal BW FS matching Current sense circuit linearity (spin-up). 2000:1 current sense. Current sense circuit linearity(at speed). 500:1 current sense. Current loop bandwidth small signal (at speed) Full scale current error Current sense matching 1% to full scale current 1% to 10% full scale Lmotor 100H to 1 H 20 5 5 5 0.5 %FS % KHz %FS %
25 to 250 mA
DAC Acceleration Control
res NL INL FS CT FSTC V oh Vol Gain1X Gain5X Resolution Differential Non-linearity Integral Non-linearity Full scale accuracy Conversion time Full Scale Temp Coefficient 1.235 0 502 2400 1.25 0.2 525 Full scale 8 0.5 1 5 10 250 1.245 0.3 554 2900 bits LSB LSB % ms ppm/C V V
Current Sense Gain at 500:1 Current Sense Gain at 2500:1
Step-up Converter
Vsu3 Step-up converter voltage (using Tripler as a doubler) above 5V. Vdd = 4.5 to 5.5 volts, Maximum load 6 V
Digital Inputs (All digital inputs are CMOS compatible)
Vih V il V oh Vol Iin High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current I in = TBD I in = TBD I out = TBD I out = TBD Tj =125C Vdd-0.6 +1 0.4 -1 30% Vdd 70% Vdd V V V V A
Power On Reset (Either low voltage detector can be disabled by trying the divider to a high voltage)
Tdelay Vref Minimum delay power OK to RESET high Voltage reference C POR_DELAY = 0.22*H 50.32 1.235 70.4 1.25 64.46 1.265 ms V
Retract
Tretract R dson I for Vretract 8/30 Retract time before brake Total switch circuit resistance 2 quadrant retract voltage VBEMF > PARK_Voltage 11 13 power low detected Tretract = 0.4 x RC TBD TBD 10 15 ms Ohms A
L6260
INTERNAL REGISTER DEFINITION System Status Register (Reg 0) Reg: 0 Name: System Status Register Type: Read only.
BIT 0 THERMAL LABEL DESCRIPTION Thermal shutdown = 1, normal = 0. One signifies that the chip temperature has exceeded the 180C. The bit will reset when the temperature falls from 180C to 140C (the hysteresis prevents rapid changing of this bit). When this bit is activated, the spindle logic will tristate both high and low side drivers to allow the disk to coast and cool down the chip. Under Voltage=0, good voltage =1. This signals whether the under voltage circuit has been activated or not. NOTE: When UV=0, the POR is activated and all serial port control logic is reset. This means that writes are impossible, however, the user can still poll the status of this register provided the logic voltage is sufficient for the logic to function. Providing mainly for testing. When the FLL is sourcing current into the charge pump capacitor this is set to 1. A 0 means that the sourcing current is disabled. Providing mainly for testing. When the FLL is sinking current from the charge pump capacitor this is set to 1. A 0 means that the sourcing current is disabled. Toggles with BEMF. Mask time currently in use = 1. When 1 this means the BEMF comparator will not sense the zero crossing at this time. A 0 means zero crossing sensing will occur. Delay time currently in use = 1. e.g. A commutation delay is active and at the end of this delay the next commutation is executed. 1=spindle is at speed (set by the first "down pulse" of the FLL. It is reset at POR. UNUSED UNUSED UNUSED UNUSED @POR 0
1
UV
0
2
FLL_UP
0
3
FLL_DOWN
0
4 5
BEMF_SENSE MASK_TIME
0 0
6 7 8 9 10 11
DELAY AT_SPEED
0 0 0 0 0 0
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L6260
VCM DAC Register (Reg 1) The VCM DAC register is used to control the current in the voice coil motor. All 10 bits are part of a resistor divider network. Bit 10 is the sign bit and logically controls the current direction through the VCM. Bit 11 selects the current sense resistor to use for current control. A 0 selects coarse and therefore only the lower sense resistor, a 1 selects the top of both resistors so that the sense resistor is the sum of the coarse and fine resistance's. Reg: 1 Name: VCM DAC Register Type: Write only.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 LABEL VDAC BIT 0 VDAC BIT 1 VDAC BIT 2 VDAC BIT 3 VDAC BIT 4 VDAC BIT 5 VDAC BIT 6 VDAC BIT 7 VDAC BIT 8 VDAC BIT 9 VCMSIGN VCMGAIN DESCRIPTION @POR LSB resistor ladder of the 10 bit VCM DAC. This is a true unsigned 0 representation of the DAC input. The value entered here is a 2s0 complement of the required DAC value encoded across eleven bits 0 (10 bit data and 1 sign bit encoded into 11 bits in 2s-complement) 0 0 0 0 0 0 MSB resistor ladder. 0 Sign bit of the above 2s-complement number. 0 This changes the gain of the VCM DAC 0
To clarify the manner in which the 2's complement is used here are some examples:
Value entered to register (0x means hex) 0x000 0x800 0x3FF 0x400 0x401 0x7FF DAC value 0x000 0x000 0x3FF 0x3FF 0x3FF 0x001 Sign + + + Gain 0 1 0 0 0 0
Spin Control Register (Reg 2) The spin control register has two functions: (1) The first (bits 0-7) is to program the current to the spindle motor to allow motor control and to preset the "at speed" voltage for the charge pump. (2) The second (bits 8-11) is to set the phase lag Reg: 2 Name: Spin Control Register Type: Write only.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 10/30 LABEL SPIN_DAC BIT 0 SPIN_DAC BIT 1 SPIN_DAC BIT 2 SPIN_DAC BIT 3 SPIN_DAC BIT 4 SPIN_DAC BIT 5 SPIN_DAC BIT 6 SPIN_DAC BIT 7 SPINDLY BIT 0 SPINDLY BIT 1 SPINDLY BIT 2 SPINDLY BIT 3
from when a BEMF zero crossing occurs to the next commutation. Nominally the delay would be 30 electrical degrees but it often is better to advanced the commutation, due to the presence of other sources of delay, related to switching. The range is from 1.875 through to 28.125 electrical degree delay at 1.875 degree increments.
DESCRIPTION Spindle current limit LSB (LSB of 8 bits written to the spindle DAC)
Spindle current limit MSB Spindle commutation delay LSB
Spindle commutation delay MSB
@POR 0 0 0 0 0 0 0 0 0 0 0 0
L6260
System Control Register A (Reg 3) Reg: 3 Name: System Control Register A Type: Write only.
BIT 0 LABEL SPIN_ENABLE DESCRIPTION Enable spindle functions (1 = enabled; 0 = Disabled). Together with VCM_ENABLE, determine the Normal, Idle or Sleep mode of operation. See Mode Table for details. Enable VCM functions (1 = enabled; 0 = Disabled). Together with SPIN_ENABLE, determine the Normal, Idle or Sleep mode of operation. See Mode Table for details. Reset spindle state machine (sequencer). 0=Reset. All spindle and FLL registers are also reset. Also used to control the charge pump (1 = off). A 0 to 1 transition of this bit increments the spindle state machine. Normally used in SEARCH mode. Must be set to 1 in RUN Mode. 1=Auto-increment enabled (RUN Mode) 0 = Auto-increment disabled (SEARCH MODE) Selects 8/12 pole motor: 1 = 8 pole, 0 = 12 pole Define Tristate, Bipolar, or Tripolar operation: See Spindle Drive Mode Table. Activated VCM Retract: 1 = retract. Programs the Spindle Speed Control Method. SPEED= 0: The L6260 operates open loop, with speed error sensing performed externally and speed effort written into the SPIN_DAC. SPEED = 1: The speed is controlled internally through the built-in control loop. Specifies electrical or mechanical cycle for the FLL control. 1 = Electrical, 0 = Mechanical Writing a 0 resets the test sequence. Must be set to 1 to allow ATEST and DTEST functions. @POR 0
1
VCM_ENABLE
0
2
SRESET
0
3 4 5 6 7 8 9
INCRE RUN_SRCH 8_12P BIP_TRIP UNI_TRIP VCMRET SPEED
0 0 0 0 0 0 0
10 11
EL_MECH TEST_COUNT_RESET
0 0
MODE OF OPERATION (REGISTER 3 BITS 0 AND 1)
SPIN_ENABLE (0) DISABLED (0) DISABLED (1) ENABLED (1) ENABLED VCM_ENABLE (0) DISABLED (1) ENABLED (0) DISABLED (1) ENABLED MODE SLEEP NOT NORMAL IDLE NORMAL DESCRIPTION MINIMUM POWER DISSIPATION. VCM IS FORCED TO A PARK CONDITION VCM DISABLED FOR REDUCED DISSIPATION NORMAL MODE OF OPERATION
SPINDLE DRIVE MODE (REGISTER 3 BITS 6 AND 7)
BIP_TRIP 0 0 1 1 UNI_TRIP 0 1 0 1 SPINDLE DRIVE MODE TRISTATE NOT DEFINED BIPOLAR TRIPOLAR 11/30
L6260
System Control Reg B (Reg 4) Reg: 4 Name: System Control Register B Type: Write only
BIT 0 1 2 3 LABEL FLLGAIN BIT 0 FLLGAIN BIT 1 FLLGAIN BIT 2 EXT_INT DESCRIPTION Frequency Locked Loop (FLL) gain control. A gain factor of 1 to 8 can be programmed, This register value varies the FLL gain by changing the Integrator Current. Bit 0 is the LSB. External or internal spindle loop feedback. This bit is programmed to 0 for BEMF feedback, 1 for external feedback. External feedback is connected via the DTEST pin, which is configured as an input in this mode. This selects a one bit pre-scaler for the internal clock, minimizing the effect of differing fequencies on the FLL and logic counters. Set to 1for 4-6MHz system clock, Set to 0 for 8-12MHz system clock This selects the signal at the SYNTH_HALL pin. When set to 0, Synth Hall pin will produce a once per BEMF crossing signal (from BEMF comparitor). Setting the bit to 1, Synth Hall pin will give a once per electrical cycle signal (from zero crossing detector). Selects the gain of the sense FET circuit of the spindle driver. 0 = Spindle is high transconductance loop gain, 1 = low gain Slew rate control Bit 0 ( LSB) Slew rate control Bit 1 Slew rate control Bit 2 (MSB) Setting this bit to 1 selects an internal 250K slew rate resistor. Setting it to 0 allows slew rate control by an external resistor. Selects between 7.5 and 15 mask time (0=15, 1=7.5) @POR 0 0 0 0
4
CLK_PRESCALE
0
5
SYNHALL
0
6 7 8 9 10 11
SFETGAIN SLEW BIT 0 SLEW BIT 1 SLEW BIT 2 SLEW BIT 3 MASK_PHASE
0 0 0 0 0
Figure 2: The following diagram explains bits 5 "SYNTH HALL" and the effect it has on the pin named SYNTH_HALL
MOTOR PHASES
Below are the three possible waveforms available from the SYNTH-HALL pin. The desired waveform is selected via "Synth Hall" bits in the System Control Register B.
Once per "BEMF Crossing" (Once per zero cross)
Once per "electrical cycle"
D94IN091
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L6260
Frequency Locked Loop Coarse Counter (Reg 5) This register contains the "coarse" FLL counter value for the FLL. This register gives a worst case Reg: 5 Name: FLL Coarse Counter Register Type: Write Only
BIT 0 1 2 3 4 5 6 7 8 9 10 11 LABEL CLATCH BIT 0 CLATCH BIT 1 CLATCH BIT 2 CLATCH BIT 3 CLATCH BIT 4 CLATCH BIT 5 CLATCH BIT 6 CLATCH BIT 7 CLATCH BIT 8 CLATCH BIT 9 CLATCH BIT 10 CLATCH BIT 11 FLL Coarse counter MSB FLL Coarse counter LSB DESCRIPTION @POR 0 0 0 0 0 0 0 0 0 0 0 0
resolution of 16s with the worst case (i.e. slowest) 4MHz clock and has a valid range of 001 to FFF hex.
Frequency Locked Loop Fine Counter (Reg 6) This register contains the "fine" counter value of the FLL. The worst case resolution (i.e. with a Reg: 6 Name: FLL Fine Counter Register Type: Write only.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 LABEL FLATCH BIT 0 FLATCH BIT 1 FLATCH BIT 2 FLATCH BIT 3 FLATCH BIT 4 FLATCH BIT 5 FLATCH BIT 6 FLATCH BIT 7 FLATCH BIT 8 FLATCH BIT 9 FLATCH BIT 10 FLATCH BIT 11
4MHz clock) is 1s. It is important that the most significant bit of this register must be a zero when a write is made. Valid writes to this register must be between 001 and 7FF hex.
DESCRIPTION FLL Fine counter LSB
@POR 0 0 0 0 0 0 0 0 0 0 0
FLL Fine counter MSB -NOTE: On a write to this register, this bit must be zero.
0
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L6260
Frequency Locked Loop Fine Error Counter (Reg 7) This register contains the error detected between Reg: 7 Name: FLL Fine Error Counter Register Type: Read Only
BIT 0 1 2 3 4 5 6 7 8 9 10 11 LABEL FINEC BIT 0 FINEC BIT 1 FINEC BIT 2 FINEC BIT 3 FINEC BIT 4 FINEC BIT 5 FINEC BIT 6 FINEC BIT 7 FINEC BIT 8 FINEC BIT 9 FINEC BIT 10 FINEC BIT 11 FLL Fine error count MSB FLL Fine error count LSB DESCRIPTION @POR 0 0 0 0 0 0 0 0 0 0 0 0
the "fine" counter value of the FLL and the actual spindle rotation time (in either mechanical or electrical mode).
CIRCUIT OPERATION General This device includes a sensorless spin driver, VCM driver, power sequencing, actuator retraction with dynamic braking, serial interface for a microprocessor and frequency locked loop for speed control. The device is register based and designed to operate via either 3V or 5V power supply. POR & Under Voltage The L6260 has an on chip power monitoring system that controls all aspects of powering up, Power On Reset of the Logic (POR), low voltage detection and power down sequencing. The circuitry consists of a Bandgap reference generator, hysteresis comparitor (for low voltage detection) and a POR timer circuit (which controls the duration of the reset). Four external pins determine the behavior of this circuit. UV1 & UV2: These two pins are provided to the user to connect to the supply voltages for
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low voltage detection. The voltage on these pins is compared to the internal Bandgap voltage to determine if a low voltage on one of the supply pins has been detected. The comparitor has built in hysteresis to reduce the effects of noise on the supply lines triggering a false POR. In other words, if either one of these inputs falls below 1.25V then the supply is regarded as being "under voltage". Normally one of these pins will be connected to allow a sensing of a 3V supply and the other to the 5V supply but this is arbitrary POR_DLY: This is a pin from which a capacitor can be connected to ground. This sets the duration of the reset state of the this chip. On power up, an internal current source charges the capacitor with a current of approximately 2mA. When the voltage on this pin reaches the bandgap voltage, the chip comes out of its reset state. The duration of this reset is determined by the size of an external capacitor to ground. POR: The POR pin is an output from the chip for resetting other devices.
L6260
APPLICATION DIAGRAM
40K FOR 0.5V RETRACT PARK/V VCM/COMP
220K
100nF
3.3 (min)
0.83 (min) VCM/I/SNS/2 VCM/PLUS
VCM coil
VCM/I/SNS/1
VCM/MINUS VVCM/2 VREFOUT VREF/MINUS 177 + BIAS CIRCUIT VCM LOGIC & DAC VOLTAGE TRIPLER VVCM/1 C1LOW C1HIGH C2LOW C2HIGH VHTRIP VLTRIP VPARKOUT VCM PARK REGISTER 0 REGISTER 1 REGISTER 2 SDIO SCLK SLOAD R/W SERIAL PORT INTERFACE REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 TEST TRISTATE ATEST DTEST
D94IN089A
330nF (Typ) 330nF (Typ) for Tripler operation not used for Doubler operation 330nF(Typ) 330nF(Typ) Connected for Doubler operation
DAC/GND 1.5nF 5V UV1 SPN-DSBL-DLY POR/DLY 220pF 4 - 12MHz POR FCLK
POWER MONITOR
CENTER TAP DRIVER
CTAP SYNTH/HALL VRECT
VCC
BEMF AMP SPINDLE BLOCK & DAC
VSPIN/1 VSPIN/2 SPN/I/SNS COIL/A COIL/B COIL/C SPIN/GND1 SPIN/GND2 1Fmin(10F Recommended) e.g. 2.5K
SPINDLE LOGIC
VPDOWN BRK/DLY SPN/I/COMP SPINDLE FLL CURRENT GENERATOR 4nF 1nF 4M
SPN/SLEW
250K typical 12.5K typical FLL/RES SPD/COMP
ANALOG TEST CIRCUIT
DIGITAL TEST CIRCUIT
CHARGE PUMP
TBD SPD/COMP/SHT 62K
10nF
15/30
L6260
Figure 3.
1.25V reference BANDGAP REFERENCE 1.25V(rising) 1.23V(falling) + UV1 pin
Comp
HYSTERESIS CONTROL
-
POR TIMER
POR pin
+ UV2 pin
Comp
-
POR-DLY pin External Cap
CPOR_DLY X 1.25 RESET DURATION = 2E -6
D94IN092
POR Parameters
SYMBOL CPORDLY Tdelay UVrise UVfall TUVD PARAMETER POR delay capacitor Delay time Rising edge reference Falling edge reference Under voltage detect to POR low MIN. 220 (*) TYP. 2200 (*) 1.25 1.23 250 MAX 4700 (*) V (**) V (**) ns UNITS pF
(*) See previous equation (**) See hysteresis transfer function below
Figure 4: Hysteresis Comparitor Transfer Characteristic for Under Voltage Detection.
1.25V (POWER GOING UP) POWER OK
UV/2
UNDER VOLTAGE DETECTED 1.23V (POWER GOING DOWN)
D94IN093
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L6260
The duration of the brake delay is defined by an external resistor and capacitor connected to the brake delay pin (BRK_DLY). Charge stored in an external capacitor connected to the Voltage Tripler (VPDOWN) is used to supply the brake delay circuit after the loss of power. During the application of power to the IC, the power on reset signal (POR) is asserted, forcing all registers to their default state (see @POR column of the register definitions) and disabling the VCM and spindle drivers. Once the supply voltage has exceeded the Voltage Good (VGT) threshold, the POR delay begins. When this delay has expired, POR is de-asserted. It is this delay whose duration is determined by an external capacitor connected to the POR_DLY pin. When a low voltage condition is detected (the supply voltage falls below the VGT) the following happens (in order):
SYMBOL tRWS tSLS tRWH tSLH tSCKD tRWD tAS tDS tAH tDH tSDZ tRWZ tPER tREC (*) DESCRIPTION R/W setup time to SCLK going high SLOAD setup time to SCLK going high R/W hold time after SCLK going high SLOAD hold time after SCLK going high SCLK high to Data Valid R/W High to Data Valid Data bit D[0] valid from HiZ Address setup time to SCLK going high Data setup time to SCLK going High Address Hold after SCLK going high Data Hold time after SCLK going High SDIO tri-state after SLOAD going High SDIO tri-state after R/W going low Minimum SCLK period Recycle - Time between successive accesses 30 30 10 10 30 30 100 100
1) Internal registers are reset and POR is asserted. 2) The automatic parking of the actuator is enabled and the brake delay starts. 3) After the brake delay expires, all low side drivers are enabled to brake the spindle. Serial Interface The serial interface is designed to be compatible with the Intel 80196 (and other similar micros) serial interface but is capable of faster data rates, up to 10 MHz. All read and write operations must consist of 16 bits, with the 80196 this would be two 8 bit accesses. The first four bits are address and the next 12 are data. If the address is a read register then the L6260 will use the SCLK from the system to shift out 12 bits of data from the addressed register. The system must provide 16 SCLK pulses to insure that the read operation completes.
MIN. 100 100 100 100 30 30 50 50 TYP. MAX. UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(*) For 10MHz system clock operation (in other words. 1 or more clock cycles of SCLK).
Serial Interface Truth Table
R/W 1 0 0 1 SLOAD 1 1 0 0 SDIO Tri-state (Port unselected) Tri-state (Port unselected) Address/Data input Data output DIRECTION Tri-state Tri-state Input Output
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L6260
Figure 5: Serial Write Timing Diagram
R/W
tRWS
tRWH
SLOAD
tSLS
tSLH
SCLK
tPER
SDIO A0
4 bit address (FIXED) A1 A2 A3 D0 D1 D2 D3 D4
12 bit data (FIXED) D5 D6 D7 D8
D94IN094
D9
D10
D11
The write cycle has a fixed address and data length. Four bits of address and 12 bits of data must be clocked in to allow the data to be loaded into the desired register. The write cycle is initiated by setting SLOAD and R/W low. Setting R/W low causes the SDIO line to be tri-stated for data input. SLOAD low enables the internal counter to increment on the rising edge of SCLK. The address and data are clocked into the chip serially Figure 6: Serial Read Timing Diagram
on each rising edge of SCLK as shown above. When both the 4 bits of address and the 12 bits of the data have been clocked in, then the addressed register will be written to with the provided data. Setting SLOAD high will clear the internal logic and tri-state the SDIO line. This also provides a way of safely aborting a write by simply forcing SLOAD high. NOTE: SLOAD must be kept low during the entire duration of the 16 write clocks.
R/W t RWS
SLOAD t SLS
SCLK
t PER
tRWD SDIO A0 INPUT A1 A2 A3 HiZ DATA INVALID D0
tSCKD OUTPUT D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D94IN095
D11
The read cycle is initiated by setting SLOAD low and clocking in a valid read address. Only four bits of address are necessary, if more than four bits are clocked in, the four MSBs will be ignored (i.e. only the first four bits will be used). If a valid address is detected, the rising edge of R/W will load the desired register into the internal serial/parallel register ready for clocking out. The
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data in the serial/parallel register is then serially clocked out on every rising edge of SCLK (LSB is clocked out first). Additional padded bits clocked out will be zero. Note: If SLOAD is set low with R/W high, the current contents of the internal shift register can be clocked out. This is useful for a "read back" of the data last written into the required register.
L6260
Figure 7: System Level Interface current, two quadrant retract, with "Spindle Powered" or "Commanded" Retract. The VCM DAC register is accessed via the serial port and allows the DAC value to be changed. This drives the VCM DAC and in turn the VCM driver. VCM Compensation and Loop Equations This information will be included in the next version of this datasheet. VCM Driver The VCM driver is capable of supplying +/- 300 mA of current although higher peak currents are acceptable for short periods of time. Closed loop control of the load current is provided by the power amplifier which consists of an error amplifier followed by an H bridge output section. The loop is compensated by an external RC network connected to the VCM_COMP pin. The direction of the current flowing in the bridge is determined by the sign bit. The H bridge has two pairs of lower drivers, only one of which is selected at a given time. Such a configuration makes it possible to choose between two values of transconductance by selecting the appropriate pair of drivers. This gain selection is accomplished using the VCM DAC Register. The VCM current sense amplifier produces a voltage which is proportional to the current flow in the voice coil. When the system is operating in a linear fashion, the steady state voltage at the VCM_I_SNS pins is approximately equal to the voltage commanded by the DAC. However, under
CLK DATA
SCLK SDIO SLOAD R/W
MICRO
CS1 R/W CS2
L6260
R/W
OTHER DATA DEVICE
CLK
D94IN096
CS
System clock (FCLK input) and its Pre Scale System clock (FCLK input) and its Pre Scale The chip must be clocked via the FCLK pin at one of two possible input frequency ranges, 4-6MHz or 8-12MHz. The required range is set up via register bit 4.3 (System Control Register B, Sys Clock Prescale bit) where 0 selects the lower frequency of 4-6MHz and a 1 selects the higher input range of 8-12MHz. VCM System The following functions are provided: Voltage controlled retract including sourcing and sinking Figure 8.
POS VCM DRIVER LOGIC DAC BIT 9 VCM DAC REGISTER (REG 1) DAC BIT 8 DAC BIT 7 DAC BIT 6 DAC BIT 5 DAC BIT 4 DAC BIT 3 DAC BIT 2 DAC BIT 1 DAC BIT 0 REF/5 DACOUT 0.0 - 0.25V + OTA VCM DAC +FINE VCM DRIVER LOGIC -COURSE -FINE +COURSE
NEG
INDUCTOR
VREF 1.25V
AUTOZERO OFFSET
COURSE/FINE
D94IN097A
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L6260
certain transient conditions, the control loop which regulates the load current can recirculate, causing the VCM_I_SNS voltage to be different from the commanded voltage. This information is useful in optimizing the command profile during a seek. The retract voltage is set by external components. The current loop bandwidth is greater than 20Khertz. VCM DAC The VCM DAC consists of 10 bits via the DAC, 1 bit sign and 1 gain bit. However, externally this can be viewed as being a single 11 bit signed value with a gain bit in the MSB position. The sign bit controls the direction of the current. Positive values of the DAC are regarded as moving the actuator towards the inside diameter (this is required for parking/braking). The magnitude is converted to a voltage which is used for closed loop regulation of the magnitude of the load current. The gain bit Retract Automatic actuator retraction is initiated when any of the following conditions occur: disabling the spin system while the VCM system is still enabled, excessive junction temperature (thermal shutdown), loss of power or microprocessor issued retract. In all cases except the loss of power, the voltage applied to the voice coil is limited by an active clamp. When power is lost, the BEMF generated by the spinning motor is rectified and applied across the voice coil to perform the parking operation. Command retract is activated via the System Control Register. VCM Gain Considerations IOUT = 0.25 setting) or IOUT = 0.25 current setting) Modes of Operation The L6260 provides for four different modes of operation, namely, Unipolar, Bipolar, Tripolar and Tristate. The Tripolar mode is included for achieving reliable start-ups in a stuck rotor condition (lengthening drive life-time). These modes are initiated via the System Control Register A, bits 7 & 8 as follows:
20/30 Bit 6 Tristate Unipolar Bipolar Tripolar 0 0 1 1 Bit 7 0 1 0 1 None 1 low side, no high side 1 low side and 1 high side 1 high side and 2 low side OR 2 high side and 1 low side # of drivers on
Spindle compensation and Loop Equations This material will be available in the next version of this datasheet. Spindle State Machine The spindle state machine provides the logic and timing signals to the spindle driver in support of the various modes of operation. When the spindle driver is disabled (via the System Control Register), the state machine puts the spindle driver into a high impedance mode and places all spindle related circuit into a reduced power mode. After a POR, at boot up or after RESET (via System Control Register) the state machine is in the known state as defined by the System Control Registers (A & B) initial condition after POR (see the @POR column of these registers). When in Unipolar mode the commutation sequence is CTR/lA, CTR/lB CTR/lC where lA = lower A driver (NOTE: Unipolar mode is only guaranteed at 3V operation). In Bipolar the commutation sequence is uA/lB (upper A and lower B), uA/lC, lC/uB, uB/lA, lA/uC and uC/lB. In Tripolar mode the state machine does not auto commutate, the microprocessor must increment the state. The sequence is uA/lBC (upper A and lower B & C), uAB/lC, uB/lAC, uCB/lA, uC/lAB and uAC/lB. The Uni/Bi/Tri-polar operation is set by two bits in the System Control Register A (3.73.8) described above (Modes of Operation). If the RUN/SEARCH bit (System Control Register A, bit 4) is false or 0 (SEARCH mode), the commutation state only increments when the INC STATE bit is strobed (also in the same register, bit 3). If the RUN/SEARCH bit is true or 1 (RUN mode) the state will increment either on a INC STATE strobe or if a qualified BEMF CROSSING occurs the state will increment after the commutation delay times out. If either THERMAL=1 (register.bit 0.0) or the POR=0, all the drivers are turned off. Tristate is the default mode of operation at power up. Period counters and delay and masking functions The period counter is an internal 11 bit register that is used to time the interval between successive zero crossings. Whenever a zero crossing is encountered, the period counter is loaded into
DAC_VALUE 1 (High current 1024 RS1
DAC_VALUE 1 1024 RS1 + RS2
(Low
L6260
both a mask counter (9 bits) and a delay counter (11 bits). The period counter is automatically reset to count the next zero crossing period. The clock used for the period and mask counters is a function of the system clock. If the FCLK (the system clock) is set to the 8-12MHz range then the period and mask counters are clocked at 1/64 of the system clock, other wise the registers are clocked at 1/32 of the system clock. The delay counter clock is programmable via the SPIN COM DLY bits in the Spin Control Register (2.8-2.11). This value is used to divide down the system clock. Since there is 60 electrical degrees between zero-crossings, the delay counter can provide 1.875 through to 28.125 electrical degree delay at 1.875 degree increments. When the period counter reaches zero, the masking of the zero-crossing starts (to avoid seeing current recirculation spikes). The delay counter then starts to count down and when it reaches zero the masking of the BEMF is released so that zero crossings can once again be detected. The masking hides the commutation of the motor which takes place during the mask. The clocking frequency of the mask and delay counters is identical. However, the delay is 11 bits and the mask only 9 bits. This means that the mask can provide 15 electrical degrees of masking time. In the System Control Register B, bit MAKE_PHASE (4.11) a bit value of zero gives this 15 electrical degrees mask time but a one gives 7.5 electrical degrees of mask. Speed Control & F.L.L. The rotational position of the motor is inferred from the BEMF wave form generated by the floating coil. The chip uses the instant of a particular zero-crossing and the period between successive zero crossings to dictate the commutation timings. The complete control loop is on chip and the speed is controlled by a reference clock FCLK. The speed control loop uses a frequency locked loop which in conjunction with an external compensation network brings the frequency of the tachometer signal to be equal to the internally generated reference frequency. The tachometer signal can either be the BEMF signal divided down to a once per mechanical revolution signal or an externally generated tachometer signal, sector burst. The output of the speed control is a current demand signal that goes to the Spindle Driver. The spindle current and the commutation delay is programmed via the Spin Control Register. There is a "fine" and a "coarse" counter that defines the speed of the motor. In more detail, the two registers are used in conjunction with two down counters which form a frequency detector that in turn creates feedback through to a charge pump to maintain the motors speed regulation. The course counter is 12 bits and is clocked at 1/64th the rate of the frequency clock (FCLK). The fine counter is clocked at 1/4th FCLK. The on chip Frequency Locked Loop (FLL) uses the electrical cycle pulses ("ec pulse") to time the motors rotation. Upon the first ec pulse, the course register's contents (loaded via the serial port) is loaded into the internal course counter is then loaded from its corresponding register. The fine counter then also immediately starts to count down. In theory (but not normally in run mode, possibly at start up) the fine counter could count down through zero an continue counting down the 2's complement of the original fine counter value. The period between the start of the course counter and the zero crossing during the fine counter operation is the programmed period. Any differences between the desired period and the ec pulse (zero crossing) is the error in the transconductance loop and corrective action is take by the charge pump. This error is a number given from a counter starting when the fine counter reaches zero and resetting when the BEMF pulse occurs. The vice versa happens if the BEMF anticipate the ending of the fine counter. The error number is loaded in REG. 7. The course and fine counter arrangement is guarateed to work in all possible circumstances (providing there is enough BEMF). For example if the zero crossing is within or outside the fine window or even if the zero crossing is in the course register range. This system will even work if the zero crossing occurs across multiple course/finecycles. The FLL has a prescaler (defined by the System Control Register bits EL_MECH and 8_12P (3.10 & 3.5) that changes the cycle counting mechanism between electrical, 8 pole or 12 pole (i.e. dividing the ec clock by 1,4 or 6) respectively. The procedure for setting the motor speed is as follows: 60 let's call T0 this quantity. T0 = SPEED T0 0.9 FCLK we obtain Ncourse e. g. Doing 64 the number to load in the course register. If this number exceed 4096 the desired speed is not achievable. Let's call ErrNc the decimal part of Ncourse doing T0 0.1 Fclk + ErrNc 16 we obtain Nfine e.g. 4 the number to load in the fine register. If this number exceed 2048 all the procedure must be repeated changing0.9 with 0.91 and 0.1 with 0.09 and so on. The spindle is enabled via the System Control Registers. The slew rate is defined by attaching a resistor to ground from the SPN_SLW pin. The current loop has a compensation RC network on the SPN_I_COMP pin and the sense resistor is attached to the SPN_I_SNS pin (to ground).
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L6260
Figure 9.
Counter value Course counter counting down FLL Course register value Fine counter counting down
Course counter counting down Fine counter counting down
FLL Fine register value
Zero crossing expected here
Time Desired period between zero crossings e.g. Actual zero crossing
"Previous" zero crossing e.g. Actual zero crossing Actual error between expected zero crossing and actual zero crossing. This value is fed into the charge pump to either speed up or slow down the rotation.
D94IN098
Figure 10.
MECH CYCLE SYSTEM STATUS (REG 0) ELEC CYCLE BEMF CYCLE MASK DELAY
HIGH SIDE PREDRIVER
SPIN CONTROL (REG 2) SPIN ENABLE RESET INC STATE RUN/SEARCH SYSTEM CONTROL (REG 3) SPIN GAIN 8/12 POLE BRAKE/BI/TRI ELEC/MECH SPEED CONTROL
12
CONTROL LOGIC
BEMF DETECT
N-MOS LOW SIDE PREDRIVER
FLL SATURATION FLL UP FLL DOWN FREQUENCY LOCKED LOOP + -
I SENSE
FLL FINE (REG 5) FLL COURSE (REG 4)
D94IN099
A Synthetic Hall output is also provided from this chip once per electrical or BEMF crossing. Using the remote current sensing of the Spindle current The remote current sensing allows the connection of the power drivers directly to ground. The bene22/30
fit here is the elimination of the external sense resistor. Under normal operation there is a 500:1 difference between the current seen on the sense pin and the current in the spindle power drivers. At start up this ratio is changed to 2500:1 (five time the normal operation). The recommended voltage at the sense pin is approximately one volt.
L6260
Example Assuming that your motor requires 200mA run current then the sense current would be 200/500 = 400A. Therefore for 1 volt at the sense pin a 2500 Ohm resistor is required (R = 1/400A). Also assuming you require 1 Amp start-up current. You need to change the sense range to 5X. This also gives 1A/2500 = 400A or 1V on a 2500 Ohm resistor. In the normal "at-speed" running the voltage at this pin will vary between 0 and 2 volts approximately (e.g. when using the FLL). When using the spindle DAC the voltage swing is from 0 to 1.25 Volts Using the Spindle DAC for Start-Up When the SPEED bit in the System Control Register A (Register 3.9) is set (to 1), the speed control is given to the DAC (i.e. control is removed from the FLL). The normal method of start-up is achieved using the DAC rather than the FLL. However the FLL can be used from zero speed with an align-and-go algorithm but start-up will be slower. The 8-bit DAC gives 4.88mV per step with a maximum voltage of 1.25V. Start-Up example Assume that one needs 1A max. start current and expects a running current of 200mA. For startup, one would program the SFETGAIN bit to 0 and the SPEED bit to 1. With this value, 1A spindle current results in 1A/3000, or 333A at the SPN_I_SNS pin. Using a 3300 resistor and programming the Spindle DAC to 1V results in the desired 1A startup current. The startup algorithm is implemented by writing Figure 11.
VDD S-A-U S-B-U S-C-U VCM-A-U VCM-B-U
into the Spindle Control Register A. Once running speed is attained, the AT_SPEED bit (System Status Register, bit 7) will go to a 1. The CPU then sets the SFETGAIN bit to 1 and the SPEED bit to 1. The normal running current of 200mA again results in 200mA/600, or 333A at the SPN_I_SNS pin. The FLL will regulate the speed with a npminal value of 1V. During "DAC control" the FLL change pump capacitor is shorted to the Spindle DAC voltage.. This allows for a smoother transition from DAC to FLL control. Power Devices When S_BIPLOAR (internal) is turned on and saturated when the spindle driver is placed in unipolar mode and has an Rdson of 1 Ohm (worst case over temperature). To support retract without requiring an isolation diode the transistor is designed so as not to conduct current from source to drain even if the supplies Vp and Vdd are at ground and the source is at a positive voltage. S_A_U, S_B_U and S_C_U are the upper spindle drive transistors. They are active whenever the drive is in bipolar mode and can be turned on in pairs in tripolar mode. To support retract without requiring an isolation diode these transistors are designed so as to not conduct current from source to drain even if the supplies Vdd and Vp are at ground and the source is at a positive voltage. S_A_L, S_B_L and S_C_L are the lower spindle drive transistors. They are active in unipolar, bipolar and tripolar drive. In linear mode the active transistor's gate drive is controlled so as to bring the current in the motor to the level set by the speed control compensation circuit or the current
VRECT
B-POLAR SR-A SPINDLE MOTOR PHASE A PHASE B CENTER TAP PHASE C SR-B SR-C
VPARK
PARK CONTROL
VCM
S-A-L
S-B-L
S-C-L
VCM-A-L
VCM-B-L
D94IN100
23/30
L6260
limit DAC. The power circuits will be as shown in the following figure 11. Synth Hall The Synth Hall pin can be programmed to provide one of two possible output wave forms (see register definitions). By setting the SYNTH_HALL bit in register System Control Register B (4.5) to zero, the signal is a once per BEMF crossing signal which has the same phase as the BEMF amplifier on chip with all the noise and false transitions removed. With this bit set to one, a once per electrical cycle signal with 50% duty cycle is produced. Brake The BRAKE mode commands a retract & then turns on the lower three drivers, S_A_L, S_B_L and S_C_L, to cause immediate braking of the spindle. Retract The retract voltage is defined by a resistor to ground from the RETRACT_V pin. Test Circuits 1) I/O Mapping Test Mode. This mode is activated by taking the TEST pin high and holdSCLK 1 2 3 4 5 6 ATEST pin carries... Nominal Bandgap Voltgage (normally 1.25V) Low Bandgap Voltage (normally 1.23V) Bias Voltage (normally 0.5V) Spindle DAC Output VCM DAC Output Temperature Shutdown Voltage (input - used to alter the point at which thermal shutdown starts operation) Connected to the A gate of the spindles Low Side Driver. Allows Rds(on) testing. Spindle mask Spindle delay FCLK/16 or FCLK/32 depending on CLK_PRESCALE bit in System Control Reg B (4.4) BEMF Comparitor output (raw) VCM predriver (A)
ing the TRISTATE pin low. This puts the device into a test mode that allows certain pins to be directly internally connected to other pins for the purpose of testing continuity of solder joints on a board. The following table defines which pins are I/O mapped and which is an input and which is an output. Notice that I/O mapped pins in one group are not physically adjacent in the package allowing more thorough testability.
INPUT PIN # 20 9 10 12 50 51 INPUT PIN NAME R/W SLOAD SCLK FCLK UV1 UV2 OUTPUT PIN # 11 11 22 22 5 5 OUTPUT PIN NAME SDIO SDIO SYNTH_HALL SYNTH_HALL POR POR
2) Digital and Analog Test Mode. This mode is activated by taking both the TEST pin and TRISTATE pin high. Once this has been done the SCLK pin of the serial interface is used to clock out digital data through the DTEST pin. Simultanously, the ATEST pin cycles through carrying different analog signals from around the chip.
DTEST pin carries... Postive/Negative incrementing of the FLL
7
VCM predriver (F).
3) Tristate Test Mode. This mode is activated by keeping the TEST pin low and taking the TRISTATE pin high. This disables the digital outputs, specifically SYNTH_HALL, POR & Sleep & Idle Functions
MODE Ready Idle Sleep INVALID STATE Spin & VCM enabled Spin enabled, VCM disabled Both spin and VCM disabled Spin disabled, VCM enabled* Spindle set to low gain
SDIO. 4) No Test Modes. All test modes are disabled by keeping the TEST pin & TRISTATE pin low
POWER LEVEL Full Reduced Minimum
POWER DISS. 20mA 10mA 2mA (typical) 5mA (max)
If the spindle is disabled while the VCM is enabled the automatic parking function is invoked.
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L6260
Figure 12: VCM Eqivalent Circuit
5V
Rn
R1
Cs
L1
+ gmn -
Ron
+ + gm1 Con
Ro1 Rc Co1
Vi
Ro X1
Vg
Vo
Cc
X (Loop opened here for analysis) Vs Rs
D96IN357
Figure 13: VCM Model
Ra Vz gm1 (Vdac) Ron gmn (Vdac) Con Ro1 gm1 (Vz) Cc Co1 Vi Rc + Vi
Vg
Cgd
Vd
Cgs gm2 (Vgs)
Ro2 Cdb Vs Rs L
R1
Rn
Csb
Cs
D96IN358
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L6260
MATCAD ANALYSIS OF l6286 VCM CURRENT CONTROL LOOP (High Gain) (User specified parameters)
Rc : = 240 103 Cc : = 240 10 R1 : = 20 L : = 1.1 10-3 Cs : = 100 10-9 Rn : = 75 Vdac : = 40 10-3 Rs : = 0.8 Id : = Vdac Rs
-9
Compensation resistance Compensation capacitance Coil resistance Coil inductance Snubber capacitace Snubber resistance DAC Voltage Sense resistance Output current Id = 0.05
(Device Parameters)
gmn : = 24.2 10-6 Ron : = 3.18 10
6
Nulling OTA transconductance, with 20% variation Nulling OTA output resistance, with 50% variation Nulling OTA output capacitance, with 10% variation Main OTA transconductance, with 20% variation Main OTA output resistance, with 50% variation Main OTA output capacitance, with 10% variation FET transconductance, with ae 10% variation gm2 = 0216 Early voltage of FET, with 5% variations FET output resistance Ro2 = 1.374 103 Predriver output resistance, with 20% variation FET source-bulk capacitance, with 10% variation FET drain-bulk capacitance, with 10% variation FET gate-drain capacitance, with 10% variation FET gate source capacitance, with 10% variation
Con : = 50 10-12 gm1 : = 1100 10 Co1 : = 1.6 10 VA = 68.7 Ro2 = VA Id
-12 -6 6
Ro1 : = 1.773 10
-12
gm2 = 0.964 Id
Ra : = 420 Csb : = 10.2 10 Cdb : = 49 10-12 Cgd : = 11 10-12 Cgs : = 156 10
-12
1ST STAGE (OTA) TRANSFER FUNCTION: i: = -1 f(n) : = 10n S(n) : = 2 i 10n n : = 2, 2.01, 7 A1: = gmn Ron gm1 Ro1 A1 = 1.501 105 fp1 = 1 2 Ron Con fz1 = gmn 2 Con Req = Ro1 Rc Ro1 + Rc
fp1 = 1.001 103 fp2 = 1 2 Req Co1
fz1 = 7.703 104 fzc = 1 2 Rc Cc
Req = 2.114 105 fpc = 1 2 (Rc + Ro1) Cc
fp2 = 4.706 105
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fzc = 6.631
fpc =0.791
L6260
S(n) S(n) 1 + 2 fzc 1 + 2 fz1 (OTA) H1(n) := A1 S(n) S(n) S(n) 1 + 2 fzc 1 + 2 fp1 1 + 2 fp2 2ND STAGE (POWER NMOS) TRANSFER FUNCTION: Zsn(n) : = Rn + ZL(n) : = 1 (snubber) Cs S(n) ZLo(n) : + LS(n) + R1 (motor) Ci : = Cgs = Cgd Co : = Cgd + Cdb
Zsn(n) ZLo(n) (load) Zsn(n) + ZLo(n)
1 + Ci*S(n) Ra - (Cgd*S(n) - gm2)
- (Cgd*S(n)
-
1 Ra 0
Co*S(n) +
1 1 + Ro2 ZL(n)
- (Cgs*S(n) + gm2) H2(n) : = 1 + Ci*S(n) Ra - (Cgd*S(n) - gm2) - (Cgd*S(n)
-
1 Ro2
0
- (Cgs*S(n)
Co*S(n) +
1 1 + Ro2 ZL(n) 1 Ro2
-
gm2 +
1 Ro2 1 1 + Ro2 Rs
- (Cgs*S(n) + gm2)
-
(Cgs + Csb)*S(n) + gm2 +
D96IN361
{H2(n) = left|[{matrix{ccol
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L6260
OPEN LOOP RESPONSE: H(n): = H1(n) H2(n) MAGNITUDE RESPONSE (dB)
(dB) 70 60 50 40 20 log( H(n) ) 30 20 10 0 -10 -20 100 1K 10K 100K 1M f(n)
|H(0)| = 1.367 104
|H2(0)| = 0.145
D96IN359
PHASE RESPONSE (%)
(dB)
D96IN360
135
90
45 arg(H(n)) 360 2 0
-45
-90
-135
-180 100 1K 10K 100K 1M f(n)
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L6260
TQFP64 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.50 1.00 0(min.), 7(max.) 0.75 0.0157 mm TYP. MAX. 1.60 0.15 1.45 0.28 0.20 0.002 0.053 0.007 0.0047 0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393 0.0295 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.0079
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
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L6260
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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